vllm.distributed.device_communicators.flashinfer_pcie_ipc_all_reduce ¶
FlashInfer PCIe CUDA-IPC all-reduce integration.
This backend targets small tensor-parallel all-reduces on a single PCIe-only node. Its workspace has a stricter lifetime and stream contract than the existing FlashInfer MNNVL/TRT-LLM all-reduce implementation, so it intentionally lives behind a separate wrapper and an opt-in environment variable.
Classes:
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FlashInferPcieIpcAllReduce–vLLM lifecycle wrapper for FlashInfer's PCIe IPC all-reduce.
Functions:
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warmup_flashinfer_pcie_ipc_allreduce–Initialize the TP PCIe IPC backend immediately before graph capture.
FlashInferPcieIpcAllReduce ¶
vLLM lifecycle wrapper for FlashInfer's PCIe IPC all-reduce.
Methods:
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capture–Move the single-stream workspace to and from the capture stream.
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setup–Allocate, tune, and prepare the exact graph-capture shapes.
Source code in vllm/distributed/device_communicators/flashinfer_pcie_ipc_all_reduce.py
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capture() ¶
Move the single-stream workspace to and from the capture stream.
Source code in vllm/distributed/device_communicators/flashinfer_pcie_ipc_all_reduce.py
setup(*, hidden_dim, dtype, capture_sizes, tune_cache) ¶
Allocate, tune, and prepare the exact graph-capture shapes.
Source code in vllm/distributed/device_communicators/flashinfer_pcie_ipc_all_reduce.py
warmup_flashinfer_pcie_ipc_allreduce(worker) ¶
Initialize the TP PCIe IPC backend immediately before graph capture.