vllm.models.minimax_m3.amd.model ¶
Inference-only MiniMax M3 (text backbone) model — AMD ROCm implementation.
Self-contained per-platform impl (mirrors deepseek_v4/amd). It is identical to ../nvidia/model.py except for RMS normalization: FlashInfer's Gemma RMSNorm kernels are CUDA-only, so MiniMAXGemmaRMSNorm here uses a native (FlashInfer-free) implementation.
The MiniMax-M3-preview config selects a single set of branches
- qk_norm_type == "per_head"
- hidden_act == "swigluoai"
- use_gemma_norm == True -> Gemma-style RMSNorm everywhere
- attention_output_gate == False
- scoring_func == "sigmoid" with a routing-bias correction term
- sparse_attention_config present -> a subset of layers run the extra "index" attention branch.
Classes:
-
MiniMAXGemmaRMSNorm–Gemma-style RMS normalization (native ROCm implementation).
-
MiniMaxM3Attention–Dense attention with per-head QK norm and partial RoPE.
-
MiniMaxM3MLP–Dense SwiGLU-OAI MLP (used by the leading dense layers).
-
MiniMaxM3MoE–Sigmoid-routed MoE block with a routing-bias correction and a shared
-
MiniMaxM3SparseAttention–Block-sparse attention layer with the lightning-indexer branch.
-
MiniMaxM3SparseForCausalLM–MiniMax M3 (sparse/dense backbone) for causal language modeling.
-
MiniMaxM3SparseForConditionalGeneration–Top-level (VL) entry point for MiniMax M3.
MiniMAXGemmaRMSNorm ¶
Bases: Module
Gemma-style RMS normalization (native ROCm implementation).
Normalizes in fp32 and scales by (1 + weight) — numerically equivalent to the FlashInfer gemma_rmsnorm / gemma_fused_add_rmsnorm kernels used in the NVIDIA path, which are unavailable on ROCm. When residual is given, the fused add + norm returns the updated (normed, residual) pair.
The fp32 normalize + scale + (optional) residual-add run in a single fused Triton pass (amd.ops.gemma_rmsnorm / gemma_fused_add_rmsnorm) instead of a chain of elementwise PyTorch kernels.
Source code in vllm/models/minimax_m3/amd/model.py
MiniMaxM3Attention ¶
Bases: Module
Dense attention with per-head QK norm and partial RoPE.
Source code in vllm/models/minimax_m3/amd/model.py
486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 | |
MiniMaxM3MLP ¶
Bases: Module
Dense SwiGLU-OAI MLP (used by the leading dense layers).
Source code in vllm/models/minimax_m3/amd/model.py
MiniMaxM3MoE ¶
Bases: Module
Sigmoid-routed MoE block with a routing-bias correction and a shared expert.
Source code in vllm/models/minimax_m3/amd/model.py
335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 | |
MiniMaxM3SparseAttention ¶
Bases: Module, AttentionLayerBase
Block-sparse attention layer with the lightning-indexer branch.
This is a merged attention layer: it owns the projections (qkv + index q/k), per-head QK norms and RoPE, and the attention-backend wiring that a generic Attention layer would normally provide — it binds the MiniMaxM3SparseBackend + main impl, registers the main paged K/V cache, and owns the lightning indexer (MiniMaxM3Indexer), which holds the index-key side cache.
The index branch (index_{q,k}proj + index_norm) feeds the sparse top-k block selection. M3 always disables the index value/output projections (sparse_disable_index_value set for every sparse layer), so index_{v,o}_proj are never created.
Source code in vllm/models/minimax_m3/amd/model.py
608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 | |
MiniMaxM3SparseForCausalLM ¶
Bases: Module, SupportsPP, SupportsEagle3
MiniMax M3 (sparse/dense backbone) for causal language modeling.
Source code in vllm/models/minimax_m3/amd/model.py
MiniMaxM3SparseForConditionalGeneration ¶
Bases: Module, SupportsMultiModal, SupportsPP, SupportsEagle3
Top-level (VL) entry point for MiniMax M3.
Owns the shared MiniMax-M3 vision tower on ROCm and delegates text generation to the AMD language-model path.
Source code in vllm/models/minimax_m3/amd/model.py
1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 | |
_aiter_moe_fused_shared_experts_enabled(is_fused_shared_expert_enabled) ¶
Whether the fused shared expert routes through aiter's grouped top-k MoE.
A strict sub-case of is_fused_shared_expert_enabled: shared-expert fusion must already be opted in (VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS) and allowed (not under expert parallelism). When additionally on gfx950 with an active aiter MoE backend, the shared expert is appended inside aiter's biased grouped top-k kernel (num_fused_shared_experts) instead of the vLLM router's torch concat. Otherwise FSE still runs via the vLLM top-k bias router.
Source code in vllm/models/minimax_m3/amd/model.py
_build_rotary_emb(config, head_dim) ¶
Build the (partial NeoX) RoPE, honoring an optional rope_scaling config.
Without scaling the cos/sin cache is sized to max_position_embeddings (524288 native); a request whose positions exceed that reads the cache out of bounds and the worker hard-crashes (no Python traceback). When rope_scaling is set (e.g. YaRN factor: 2 to reach 1M), thread it into get_rope so the proper scaled embedding is built and its cache covers original_max_position_embeddings * factor positions. Default behavior (no scaling) is unchanged. Shared by the dense and sparse attention layers, and the index branch reuses the returned module.
Note: for the VL checkpoint, set rope_scaling on the text config (--hf-overrides '{"text_config":{"rope_scaling":{...}}}') -- that is the config the decoder reads here; a top-level override does not reach it.
Source code in vllm/models/minimax_m3/amd/model.py
_is_moe_layer(config, layer_id) ¶
Whether this layer's MLP is a sparse MoE block (vs a dense MLP).
Source code in vllm/models/minimax_m3/amd/model.py
_kv_insert_operand(t) ¶
K or V operand for aiter.reshape_and_cache, without a needless copy.
The AITER sparse-PA insert takes K and V as column slices of the fused [q | k | v | index_q | index_k] projection, so they are row-strided views and never contiguous. reshape_and_cache does not need them to be: it passes key.stride(0) to the kernel as the row pitch and reads key[token_idx * key_stride + i] for i over num_heads * head_size, so the only requirement is that the trailing (num_heads, head_size) block be contiguous within a row, which such a slice always satisfies. Any other layout falls back to a copy.
Source code in vllm/models/minimax_m3/amd/model.py
_should_skip_index_topk(config, layer_id) ¶
ATOM index_topk_freq (cross-layer index sharing).
Only 1 of every index_topk_freq sparse-attention layers recomputes the lightning-indexer top-k block selection; the rest reuse the selection the preceding compute layer wrote into the shared topk_indices_buffer this same forward pass. This cuts the indexer score + top-k cost ~freqx with negligible accuracy impact (adjacent sparse layers pick nearly the same blocks; ATOM validated GSM8K with freq=4). Gated by use_index_cache; enable via --hf-overrides '{"use_index_cache": true, "index_topk_freq": 4}'.
Source code in vllm/models/minimax_m3/amd/model.py
_sparse_attention_layer_ids(config) ¶
Layer ids whose attention runs the extra sparse "index" branch.
Source code in vllm/models/minimax_m3/amd/model.py
_sparse_attention_layer_ordinals(config) ¶
Map each sparse-attention layer id to its ordinal among sparse layers.